Liquid crystal display device and associated method for improving holding characteristics of an active element during a vertical blanking interval

ABSTRACT

A liquid crystal display device includes pixels, gate lines and source lines, active elements, a gate driver circuit, a source driver circuit, and a timing controller circuit. The source driver circuit conducts a prescribed operation of supplying the source signals of positive polarity and negative polarity having a prescribed voltage to the source lines during a vertical blanking interval, and electrically cutting the source lines off after the supply of the source signals while establishing a short circuit between adjoining source lines supplied with the source signals of opposite polarities, thereby causing the source lines to hold a prescribed DC voltage value.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to liquid crystal display devices andmethods of driving the same and, in particular, to a liquid crystaldisplay device including active elements and a method of driving thesame.

2. Description of the Background Art

A description of the structure and the operating principles of a typicalactive matrix TFT (Thin Film Transistor) liquid crystal display device(hereafter simply called a liquid crystal display device) is provided.The liquid crystal display device has pixels arranged in a matrix on atranslucent substrate, and gate lines and source lines interconnected tosurround the pixels. Provided at the intersection of each gate line andeach source line is a TFT, an active element, whose drain electrode isconnected to a pixel. An opposed substrate is provided in an opposedposition to the array substrate on which the pixels are formed. Theopposed substrate and the array substrate have a liquid crystalinterposed therebetween. The opposed substrate has opposed electrodesformed thereon, which are set to common potential. It may therefore beunderstood that the drain electrode of the TFT is connected tocapacitance that is connected to the common potential of the opposedelectrode. The liquid crystal capacitance is typically represented asC_(LC). A storage capacitor C_(S) is also formed in parallel to theliquid crystal capacitance C_(LC) in the liquid crystal display device.

The gate lines are connected to a gate driver which is supplied with astart pulse STV and a vertical clock CLKV from a timing controller. Thegate driver shifts the start pulse STV at timing of the vertical clockCLKV by a shift register, and level-shifts the contents of the shiftregister by an output buffer, to output desired gate potentials Vgh(gate-ON voltage) and Vgl (gate-OFF voltage). A gate line is selectedonce during one vertical interval, and the selected period is of almostthe same length as one horizontal interval. The gate line is in an ONstate during that period, and in an OFF state during the other periods.

The source lines are connected to a source driver. The source linesthemselves have parasitic capacitance. The source driver is suppliedwith a start pulse STH, a data signal DATA, and a horizontal clock CLKHfrom the timing controller. With the start pulse STH as a referencepoint, the source driver captures the data signal DATA at timing of thehorizontal clock CLKH successively and stores them in a shift dataregister. The source driver also subjects the value stored in the shiftdata register to D/A conversion by a D/A converter based on a latchsignal LP supplied from the timing controller, and outputs it to thesource lines via an output buffer.

When the data signal DATA is subjected to D/A conversion, a POL signalsupplied from the timing controller is latched by the latch signal LP,and the output from the D/A converter has a voltage of positive polarityor negative polarity due to the polarity of the POL signal in the sourcedriver. As well known, a liquid crystal deteriorates upon being keptapplied with DC voltage, resulting in a fault such as image persistence.Therefore, the liquid crystal display device adopts a driving system ofinverting the polarity of voltage applied to the liquid crystal atregular intervals.

One vertical period is the most commonly adopted polarity inversionperiod of a liquid crystal display device. Frame inversion of the entirescreen having the same polarity is a spatial inversion method during onevertical period. With frame inversion, however, a subtle differencebetween positive-polarity applied voltage and negative-polarity appliedvoltage will be visually identified as flicker. Therefore, row-inversiondrive with inversion at intervals of n rows, column-inversion drive withinversion at intervals of m columns, and n×m dot inversion drive withinversion at intervals of n rows and m columns, each of which has a finesame-polarity area spatially mixed, are widely adopted.

One vertical interval includes a vertical effective interval and avertical blanking interval. The panel is scanned in a vertical directionduring the vertical effective interval, and no gate line is selectedduring the vertical blanking interval. The source lines hold a potentialwritten in the last line during the vertical blanking interval if leftuncontrolled. A short vertical blanking interval presents no problem,but a long one has adverse effects such as described below.

A TFT does not completely become OFF and leaks to some extent when notselected. The amount of leakage depends on a drain-source voltage V_(DS)of the TFT. Thus when the potential of a source line is at extremelyhigh voltage during the vertical blanking interval, a pixel A writtenwith a voltage of positive polarity approaches the extremely highvoltage relatively gently, while a pixel B having the same gradation asthe pixel A and written with a voltage of negative polarity approachesthe extremely high voltage suddenly. With such change, the pixel A growsdark while the pixel B grows light (in normally white mode). When theimage is a still image, the same thing occurs with opposite polaritiesin the next frame. That is, when the potential of a source line is atextremely low voltage during the vertical blanking interval, the pixel Awritten with a voltage of negative polarity grows dark while the pixel Bwritten with a voltage of positive polarity grows light.

The above problem is caused by not only the TFT leakage but parasiticcapacitance C_(DS) across the drain and source. When the source linesare inverted at intervals of n rows, pixel potential varies constantlyunder the influence of the parasitic capacitance C_(DS). Thus a pixelpotential influenced by the potential of the last row is held during thevertical blanking interval, resulting in the same problem as describedabove.

The above problem causes a difference in shade between the pixels A andB, and also causes an effective DC component to be applied to the liquidcrystal, which leads to liquid crystal deterioration. To reduce powerconsumption, the liquid crystal display device adopts a low framefrequency driving system in which an image is temporarily written andthen held for a couple of vertical periods for a still image, forexample. The low frame frequency driving system is adopted particularlyfor liquid crystal display devices intended for battery-driven mobileequipment. In a liquid crystal display device with the low framefrequency driving system, a blanking interval is significantly extended,which further encourages the above problem.

To address the problem, Japanese Patent Application Laid-Open Nos.5-313607 (1993) and 2003-173 are proposed.

Japanese Patent Application Laid-Open No. 5-313607 adopts inversiondrive of inverting voltage applied to source lines during a verticalblanking interval. This method, however, increases power consumptionbecause the source lines need to be driven during the vertical blankinginterval when they do not originally need to be driven. The methoddisclosed in JP 5-313607 thus cannot be adopted for a liquid crystaldisplay device with the low frame frequency driving system for low powerconsumption.

Japanese Patent Application Laid-Open No. 2003-173 discloses a method oftemporarily charging source lines to common potential after the start ofa vertical blanking interval. This method is adaptable to the low framefrequency driving system. Yet this method requires a separate chargingcircuit which increases the circuit size.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a liquid crystaldisplay device capable of improving the holding characteristics of anactive element during a vertical blanking interval with low powerconsumption and without increasing the circuit size, and a method ofdriving the same.

In an aspect of the present invention, a liquid crystal display deviceincludes pixels, gate lines and source lines, active elements, a gatedriver circuit, a source driver circuit, and a timing controller. Thepixels are arranged in a matrix on a translucent substrate. The gatelines and the source lines are provided in a corresponding manner to thepixels. The active element is at an intersection of each of the gatelines and each of the source lines, and has a drain electrode connectedto the pixel. The gate driver circuit supplies a gate signal to the gatelines. The source driver circuit supplies a source signal to the sourcelines so that source signals having a positive polarity voltage relativeto a common potential of the pixels and source signals having a negativepolarity voltage are almost equal in number during one horizontalinterval. The timing controller circuit supplies prescribed signals tothe gate driver circuit and the source driver circuit to control thecircuits. The source driver circuit conducts a prescribed operation ofsupplying the source signals of positive polarity and negative polarityhaving a prescribed voltage to the source lines during a verticalblanking interval, and electrically cutting the source lines off afterthe supply of the source signals while establishing a short circuitbetween adjoining the source lines supplied with the source signals ofopposite polarities, thereby causing the source lines to hold aprescribed DC voltage value.

According to the liquid crystal display device of the present invention,the source driver circuit supplies the source signals of positivepolarity and negative polarity having a prescribed voltage to the sourcelines during a vertical blanking interval, and electrically cuts thesource lines off after the supply of the source signals whileestablishing a short circuit between adjoining the source lines suppliedwith the source signals of opposite polarities, thereby causing thesource line to hold a prescribed DC voltage value. This increases theholding characteristics of the active element during the verticalblanking interval with low power consumption and without increasing thecircuit size.

Another aspect of the present invention is directed to a method ofdriving a liquid crystal display device, the device including: pixelsarranged in a matrix on a translucent substrate; gate lines and sourcelines provided in a corresponding manner to the pixels; an activeelement at an intersection of each of the gate lines and each of thesource lines, the active element having a drain electrode connected tothe pixel; a gate driver circuit supplying a gate signal to the gatelines; a source driver circuit supplying a source signal to the sourcelines so that source signals having a positive polarity voltage relativeto a common potential of the pixels and source signals having a negativepolarity voltage are almost equal in number during one horizontalinterval; and a timing controller circuit supplying prescribed signalsto the gate driver circuit and the source driver circuit to control thecircuits. The method of driving the liquid crystal display deviceincludes an output step, a short-circuit step, and a holding step. Theoutput step supplies the source signals of positive polarity andnegative polarity having a prescribed voltage to the source lines duringa vertical blanking interval by the source driver circuit. Theshort-circuit step of electrically cuts the source lines off from thesource driver circuit after the supply of the source signals whileestablishing a short circuit between adjoining the source lines suppliedwith the source signals of opposite polarities after the output step.The holding step causes the source lines to hold a prescribed DC voltagevalue after the short-circuit step.

According to the method of driving the liquid crystal display device ofthe present invention, the source signals of positive polarity andnegative polarity having a prescribed voltage are supplied to the sourcelines during a vertical blanking interval, and the source lines areelectrically cut off after the supply of the source signals whileestablishing a short circuit between adjoining the source lines suppliedwith the source signals of opposite polarities, thereby causing thesource line to hold a prescribed DC voltage value. This increases theholding characteristics of the active element during the verticalblanking interval with low power consumption and without increasing thecircuit size.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows potential variations in source line according to a firstpreferred embodiment of the present invention;

FIG. 2 is a block diagram of a liquid crystal display device accordingto the first preferred embodiment of the present invention;

FIG. 3 is a circuit diagram of the liquid crystal display deviceaccording to the first preferred embodiment of the present invention;

FIG. 4 is an illustration for explaining drive of the liquid crystaldisplay device according to the first preferred embodiment of thepresent invention;

FIG. 5 is a circuit diagram of a source driver according to the firstpreferred embodiment of the present invention;

FIG. 6 is an illustration for explaining drive of the source driveraccording to the first preferred embodiment of the present invention;

FIG. 7 is an illustration for explaining pixel holding potentialaccording to the first preferred embodiment of the present invention;

FIG. 8 is an illustration for explaining drive of the liquid crystaldisplay device according to the first preferred embodiment of thepresent invention;

FIG. 9 is an illustration for explaining fluctuations in feed-throughvoltage according to a second preferred embodiment of the presentinvention;

FIG. 10 is an illustration for explaining fluctuations in source holdingpotential according to the second preferred embodiment of the presentinvention; and

FIG. 11 is a block diagram of a timing controller according to thesecond preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Preferred Embodiment

FIG. 1 shows potential variations in source line of a liquid crystaldisplay device according to a first preferred embodiment. FIG. 2 is ablock diagram of the liquid crystal display device according to thisembodiment. Referring to FIG. 2, the structure of the liquid crystaldisplay device according to this embodiment is first described. Thestructure of a typical active matrix TFT liquid crystal display devicemay be used for the liquid crystal display device according to thisembodiment.

The liquid crystal display device shown in FIG. 2 has pixels 2 arrangedin a matrix on a translucent substrate 1, and gate lines 3 and sourcelines 4 interconnected to surround the pixels 2. Provided at theintersection of each gate line 3 and each source line 4 is a thin filmtransistor (TFT 5), an active element, whose drain electrode 6 isconnected to a pixel element. An opposed substrate (not shown) isprovided in an opposed position to the substrate 1 on which the pixels 2are formed. The opposed substrate and the substrate 1 have a liquidcrystal interposed therebetween, to form a liquid crystal panel. Theopposed substrate has opposed electrodes formed thereon, which are setto common potential V_(COM). Since a liquid crystal is a dielectric, itmay be understood that capacitance 7 having one end connected to thecommon potential V_(COM) of the opposed electrode is connected to thedrain electrode 6 of the TFT 5.

FIG. 3 is a circuit diagram in the vicinity of the TFT 5. In FIG. 3, thecapacitance 7 includes liquid crystal capacitance C_(LC) and a storagecapacitor C_(S) in parallel to the liquid crystal capacitance C_(LC).FIG. 3 also illustrates parasitic capacitance C_(GD) generated acrossthe gate and drain of the TFT 5, and parasitic capacitance C_(DS)generated across the drain and source.

Referring back to FIG. 2, the gate lines 3 are connected to a gatedriver 8 which is supplied with a start pulse STV and a vertical clockCLKV from a timing controller 9. The gate driver 8 shifts the startpulse STV at timing of the vertical clock CLKV by a shift register 10,and level-shifts the contents of the shift register 10 by an outputbuffer 11, to output desired gate potentials Vgh (gate-ON voltage) andVgl (gate-OFF voltage).

The source lines 4 are connected to a source driver 12. The source lines4 themselves have parasitic capacitance. The source driver 12 issupplied with a start pulse STH, a data signal DATA, and a horizontalclock CLKH from the timing controller 9. With the start pulse STH as areference point, the source driver 12 captures the data signal DATA attiming of the horizontal clock CLKH successively and stores them in ashift data register 13. The source driver 12 also subjects the valuestored in the shift data register 13 to D/A conversion by a D/Aconverter 14 based on a latch signal LP supplied from the timingcontroller 9, and outputs it to the source lines 4 via an output buffer15. When the source driver 12 receives an analog signal, namely, whenthe data signal DATA is not a digital signal but an analog signal, thesource driver 12 may have a sample-and-hold circuit instead of the shiftdata register 13, without a D/A converter.

When the data signal DATA is subjected to D/A conversion, a POL signalsupplied from the timing controller 9 is latched by the latch signal LP,and the output from the D/A converter 14 has a voltage of positivepolarity or negative polarity due to the polarity of the POL signal inthe source driver 12.

Drive of applying voltage of positive polarity or negative polarity to aliquid crystal is described. FIG. 4 is a schematic diagram of the orderof voltage applied to a normally white (NW) liquid crystal. For brevity,it is assumed that a liquid crystal display device shown in FIG. 4 iscapable of four-gradation display. The diagram is to be read by changingbetween black and white for a normally black (NB) mode. When commonpotential (V_(COM)) is set as an intermediate potential between voltagesV₄ and V₅, a voltage applied to the liquid crystal is expressed asV_(n)−V_(COM) (n=1 to 8). Accordingly, a positive voltage is applied tothe liquid crystal with a voltage V_(n) (n=1 to 4) of positive polarity,and a negative voltage is applied to the liquid crystal with a voltageV_(n) (n=5 to 8) of negative polarity. An optical response of the liquidcrystal, which is determined by the absolute value of the appliedvoltage, is of the same gradation with any of the combinations of n=(1,8), (2, 7), (3, 6), and (4, 5). In short, applied voltages of thesecombinations are equal in absolute value.

Referring to FIG. 4, the aforementioned leakage of the TFT 5 isdescribed. When the potential of the source line 4 is at the extremelyhigh voltage V₁ during the vertical blanking interval, a pixel A writtenwith the voltage V₃ of positive polarity approaches the voltage V₁relatively gently, while a pixel B having the same gradation as thepixel A and written with the voltage V₆ of negative polarity approachesthe voltage V₁ suddenly. With such change, the pixel A grows dark whilethe pixel B grows light (in normally white mode). When the image is astill image, the same thing occurs with opposite polarities in the nextframe. That is, when the potential of the source line 4 is at theextremely low voltage V₈ during the vertical blanking interval, thepixel A at the voltage V₆ grows dark while the pixel B at the voltage V₃grows light.

In this embodiment, the polarity of output from the source driver 12 isinverted at intervals of m lines, to drive the panel with n×m dotinversion or m-column inversion as a whole. Such structure can beattained by using a line-by-line inversion type source driver ICdistributed most widely on the market. Further, the source driver 12according to this embodiment has the function of neutralizing the chargeaccumulated in the source lines 4 by establishing a short circuitbetween outputs of different polarities. This is typically called chargesharing, a function of temporarily neutralizing the charge of the sourceline 4 charged to the opposite polarity in a row where the polarityapplied to the liquid crystal changes, thereby suppressing powerconsumption for charging the source line 4.

FIG. 5 illustrates an equivalent circuit in an output stage of thesource driver 12 having the charge sharing function according to thisembodiment. In the source driver 12 shown in FIG. 5, odd-numbered (2n+1,2(n+1)+1) output buffers 15 and even-numbered (2n, 2(n+1)) outputbuffers 15 are opposite to each other in output polarity. In the latterstage of each of the output buffers 15, a normally closed switch (NCSW20) that opens with the control signal (latch signal LP) being High isconnected in series relative to the source line 4. Additionally, in thesource driver 12 shown in FIG. 5, the latter stage of the odd-numbered(2n+1, 2(n+1)+1) output buffer 15 is connected to the latter stage ofthe even-numbered (2n, 2(n+1)) output buffer 15 with a normally openedswitch (NOSW 21) that closes with a signal from an AND circuit 16 beingHigh.

The NCSW 20 is controlled by the latch signal LP, and the NOSW 21 iscontrolled by the ANDed signal from the AND circuit 16 that receives thelatch signal LP and a CSMODE signal. When the CSMODE signal is Low, theNOSW 21 connected between the output buffers 15 does not operate, thusnot effecting charge sharing. At this time, when the latch signal LP toinitiate D/A conversion (conversion starts on the leading edge) becomesHigh, the NCSW 20 is released to stop ineffective output during thatinterval. When the CSMODE signal is High, outputs of adjoining oppositepolarities are shorted during an interval when the latch signal LP isHigh, thus neutralizing the charge in the source line 4.

The CSMODE signal may not be controlled from outside in some of thesource driver ICs on the market. Yet the scope of the present inventionwill not be limited by the presence or absence of outside control of theCSMODE signal as long as the charge sharing function works.

Referring to FIG. 6, a control signal of the liquid crystal displaydevice according to this embodiment is described. The CSMODE signal isnot particularly illustrated in FIG. 6 because the present invention isviable even when there is no CSMODE signal that is controllable fromoutside, or when the CSMODE signal is controllable from outside and isdynamically controlled from the timing controller 9, or when the CSMODEsignal is fixed to High.

In FIG. 6, the lateral axis represents time, and waveforms indicatewaveforms of signals supplied to the source driver 12. An f-framevertical effective interval on the left in FIG. 6 is a normal drivinginterval. During a last-row horizontal effective interval in the f-framevertical effective interval, the data signal DATA of the last row istransferred to the source driver 12. The latch signal LP rises after thetransfer to initiate D/A conversion. Upon fall of the latch signal LP, adesired voltage is output from the output buffer 15 to the source line4. The other rows are subjected to the same process as the last rowillustrated in FIG. 6.

Next, an f-frame vertical blanking interval shown in FIG. 6 has a firstsignal interval during which the data signal DATA is transferred to thesource driver 12 as in the horizontal effective interval. The datasignal DATA transferred during this interval is not based on an inputsignal to the timing controller 9, but is separately prescribed datadescribed later. The f-frame vertical blanking interval then has asecond signal interval during which the latch signal LP becomes High toinitiate D/A conversion.

The f-frame vertical blanking interval subsequently has a third signalinterval during which the latch signal LP becomes Low to output the D/Aconverted data to the source line 4. The f-frame vertical blankinginterval has a fourth signal interval after that during which the latchsignal LP becomes High and is held until immediately before the start ofthe next frame (f+1). The POL signal and the start pulse STH are alsoillustrated in FIG. 6.

Referring to FIG. 1, a description is provided of potential variationsin the source line 4 through drive during the f-frame vertical blankinginterval shown in FIG. 6. Note that the potential variations in thesource line 4 are delayed almost by a period that combines a horizontaleffective interval and an interval during which the latch signal LP isHigh, relative to timing of the vertical effective interval and verticalblanking interval shown in FIG. 6. The reason for the delay is that thedata signal DATA of the last row is actually output to the source line 4upon fall of the latch signal LP that rose immediately after thecompletion of capturing the last data signal DATA, and that pixels arecharged in the last row almost over one horizontal interval from thefalling point of time. FIG. 1 depicts the f-frame vertical effectiveinterval and the f-frame vertical blanking interval based on thepotential of the source line 4, and is thus different from FIG. 6. Tofacilitate understanding, the f-frame vertical effective interval(source voltage) and the like are written on the lower portion in FIG.1, with the corresponding signal intervals of FIG. 6 on the upperportion.

First, during the f-frame vertical effective interval, an output voltagecorresponding to the data signal DATA of the last row is applied to thesource line 4. Then, the latch signal LP becomes High to effect thecharge sharing function (the CSMODE signal becomes High) during thesecond signal interval in the f-frame vertical blanking interval, thusneutralizing the charge in the source line 4. The potential of thesource line 4 thus converges to an intermediate potential of the sourceline 4 potential held in the last row. By the time of transition to thesecond signal interval, all the gate lines 3 have entered an OFF state.

Then, the latch signal LP falls during the third signal interval,causing the data signal DATA having been transferred during the firstsignal interval in the f-frame vertical blanking interval to be D/Aconverted and output to the source line 4 (setting data outputinterval). Next, the latch signal LP becomes High during the fourthsignal interval to effect the charge sharing function, causing thepotential of an adjoining source line 4 charged up to that point toconverge to an almost intermediate potential (short circuit interval).The converged intermediate potential is subsequently held (holdinginterval). It is assumed that the capacitance of the source line 4 isequal in any position. After the convergence, the charge sharingfunction may be terminated (by reducing the CSMODE signal to Low) toplace the source line 4 in a floating state, or may be maintained. Theresult is the same with or without the termination of the charge sharingfunction, because two adjoining source lines 4 enter a floating statefrom the other portions.

A first-row horizontal effective interval of an f+1 frame startssubsequently, during which the source driver 12 temporarily reduces thelatch signal LP to Low in preparation for capturing the next data signalDATA. The output buffer 15, in which data updated in the previousinterval (first signal interval) remains, then outputs a voltagedifferent only in polarity due to a change in the POL signal during thefirst-row horizontal effective interval. This operation may varydepending on the type of driver IC on the market.

At the completion of the first-row horizontal effective interval of thef+1 frame, a voltage corresponding to the data signal DATA capturedduring that interval is output to the source line 4 (start of an f+1frame vertical effective interval of the source voltage). At this time,gates in the first row enter an ON state to initiate sequentialscanning.

In the course of the processes of the first to fourth signal intervalsas shown in FIG. 6 during the subsequent vertical blanking interval, thesource voltage initially fluctuates to some extent, but can hold aconstant DC voltage thereafter. In addition, no change is made duringthis interval to charge and discharge of the source line 4 or to thecontrol signal. This means very little power consumption during thevertical blanking interval.

Meanwhile, with the use of the charge sharing function, the potential ofthe source line 4 after charge sharing is placed almost at midpoint ofthe potential of an adjoining source line 4 charged with voltage of adifferent polarity. Thus the potential during the holding interval shownin FIG. 1 (source holding potential) may be set to the common potentialby calculating the data signal DATA written during the first signalinterval backwards from the actually output voltage, using an expressionof (positive polarity voltage+negative polarity voltage)/2=commonpotential. With commonly available source driver ICs having gradationresolution from 1/63 to 1/255, the selection of an optimum combinationof voltages from a variety of combinations allows the source holdingpotential to be set to the common potential with considerably highaccuracy.

The setting of a voltage of positive polarity and negative polarity tobe output during the vertical blanking interval may be specifically madeby using data stored in a non-volatile memory in the timing controller 9or data supplied from an external setting port and the like as gradationdata to be output during that interval.

When the vertical blanking interval is significantly long, the potentialof the source line 4 in a floating state from the other portions mayvary due to leak current. In such a case, the first to fourth signalintervals shown in FIG. 6 are conducted several times during thevertical blanking interval, thus supplying a prescribed data signal DATAregularly to the source driver 12 to maintain the source holdingpotential.

A detailed description is now provided about where to set the sourceholding potential. While the TFT 5 is OFF, holding potential of thecorresponding pixel 2 (pixel holding potential) fluctuates in slightlydifferent ways depending on components of leakage from the TFT 5 andother parts, and components from the parasitic capacitance C_(DS).

The first case is when the TFT 5 and other parts do not leak at all andonly the components from the parasitic capacitance C_(DS) have aninfluence. FIGS. 7 and 8 illustrate fluctuations in pixel holdingpotential according to this embodiment. The upper graph of FIG. 7 isdirected to the pixel holding potential in a first row of a certaincolumn, and the lower graph is directed to the pixel holding potentialin a second row of the same column as the upper graph. FIG. 8 showsparts of the pixel holding potentials in the first and second rows thatare superimposed, with corresponding gate line potentials.

It is assumed with respect to the source lines shown in FIG. 7 thatpolarity is inversed row by row and an image displayed is a raster imagehaving some kind of gradation (the entire screen having the samegradation). It is also assumed that a vertical blanking interval is notparticularly conducted, and the data signal DATA in the last row is keptoutput.

Referring to FIGS. 7 and 8, when a gate in the first row opens, thecorresponding TFT 5 enters an ON state, causing the pixel 2 to becharged up to a positive source potential. At this time, the pixelholding potential converges to the positive source potential smoothlywith a time constant depending on the mobility of the TFT 5. When thegate is then turned off, the pixel holding potential decreases due to ACcoupling to the gate potential under the influence of the parasiticcapacitance C_(GD). The decreased voltage is generally calledfeed-through voltage (ΔV_(CGD)). Subsequently, since the TFT 5 of thepixel 2 in the first row is in an OFF state, the pixel electrode is in afloating state in terms of direct current (because of the assumed noleakage).

However, due to components of the structural capacitance from the sourceline 4 arranged next to the pixel 2 and the parasitic capacitance C_(DS)of the TFT 5, the pixel 2 undergoes potential fluctuation (ΔV_(CDS)) inproportion to the change in the source line 4. An average potentialV_(AVEn) of a pixel in an “n-th” row during one vertical period at thistime can be expressed as the following equation 1 which excludes anaverage in the written row for brevity of calculation. For a liquidcrystal display device having the total number of rows of approximatelyseveral hundreds to a thousand, the written row has an influence ofapproximately 1/the total number of rows, and is therefore negligible.

$\begin{matrix}{V_{AVEn} = {{V_{sn} - {\Delta\; V_{CGD}} + {\frac{k}{T_{V}}{\sum\limits_{i}{\Delta\; V_{CDS}\Delta\; T_{i}}}}} = {V_{sn} - {\Delta\; V_{CGD}} + {\frac{k}{T_{V}}{\sum\limits_{i}{\left( {V_{si} - V_{sn}} \right)\Delta\; T_{i}}}}}}} & \left\lbrack {{Equation}\mspace{14mu} 1} \right\rbrack\end{matrix}$

The sign i in the equation 1 represents an index of a position where thesource line fluctuates other than the “n-th” row. The equation 1 adds upinfluences of source potential fluctuations in the position other thanthe “n-th” row over one vertical period. The sign V_(sn) represents thesource potential in a position of the “n-th” row, the sign k representsa constant obtained by dividing the parasitic capacitance C_(DS) by thetotal capacitance of the pixel other than the parasitic capacitanceC_(DS), the sign T_(V) represents the vertical period, and the signΔT_(i) represents time during which source potential in the “i-th” rowis constant. With the assumption that the entire screen has the samegradation with no vertical blanking interval, and an average voltage ofpixels written with positive polarity is represented as V_(AVE+) and anaverage voltage of pixels written with negative polarity is representedas V_(AVE−), the equation 1 can be written as the following equation 2:

$\begin{matrix}{{V_{{AVE} +} = {{V_{s +} - {\Delta\; V_{CGD}} + {\frac{k}{2}\left( {V_{s -} - V_{s +}} \right)}} = {V_{s +} - {\Delta\; V_{CGD}} - {\frac{k}{2}\left( {V_{s +} - V_{s -}} \right)}}}}{V_{{AVE} -} = {V_{s -} - {\Delta\; V_{CGD}} + {\frac{k}{2}\left( {V_{s +} - V_{s -}} \right)}}}} & \left\lbrack {{Equation}\mspace{14mu} 2} \right\rbrack\end{matrix}$

The sign V_(S+) in the equation 2 represents a positive sourcepotential, and the sign V_(S−) represents a negative source potential.Also in the equation 2, the numbers of changes in positive polarity andnegative polarity other than the written row are almost equal and arethus approximated.

The first term on the right side of the equation 2 represents chargingpotential to the source line, and the second term represents a reductionby the same feed-through voltage (ΔV_(CGD)) with both positive andnegative polarities. The third term on the right side of the equation 2indicates that positive polarity renders the potential negative toreduce the average voltage of the pixel, and negative polarity rendersthe potential positive to increase the average voltage of the pixel,thus reducing amplitude (pixel applied voltage). The equation 2 showsthat the common potential V_(COM) is at midpoint between the positivesource potential V_(S+) and the negative source potential V_(S−). Thecommon potential V_(COM) is thus set to a potential reduced by thefeed-through voltage (ΔV_(CGD)) from a source intermediate potentialshown in FIG. 7. The equation 2 further shows that, in consideration ofthe amplitude reduction in the third term on the right side of theequation 2, the amplitude of the positive source potential V_(S+) andthe negative source potential V_(S−) should be set to a value that canobtain desired gradation.

Next, the source holding potential during the vertical blanking intervalis described. Assuming that the sign T_(B) represents the verticalblanking interval and the sign V_(SB) represents the source holdingpotential during that interval, average potentials of positive polarityand negative polarity can be expressed as the following equation 3:

$\begin{matrix}{{V_{{AVE} +} = {V_{s +} - {\Delta\; V_{CGD}} - {\frac{k}{2}\left( {V_{s +} - V_{s -}} \right)} + {\frac{k}{T_{V}}\left( {V_{SB} - V_{s +}} \right)T_{B}}}}{V_{{AVE} -} = {V_{s -} - {\Delta\; V_{CGD}} + {\frac{k}{2}\left( {V_{s +} - V_{s -}} \right)} + {\frac{k}{T_{V}}\left( {V_{SB} - V_{s -}} \right)T_{B}}}}} & \left\lbrack {{Equation}\mspace{14mu} 3} \right\rbrack\end{matrix}$

When the vertical blanking interval T_(B) is long as in the low framefrequency driving system, a fourth term component on the right side ofthe equation 3 increases and becomes nonnegligible. Although theinfluence of the fourth term should be reduced by setting the fourthterm to zero, no source holding potential V_(SB) exists that becomeszero relative to both the positive source potential V_(S+) and thenegative source potential V_(S−). If potentials fluctuate by the sameamount with opposite polarities, the amplitude changes but the amountsof change become equal. This cancels out a DC component (deviation ofamplitude) applied to the liquid crystal, thereby improving imagepersistence. The conditions of such source holding potential V_(SB) areexpressed as the following equation 4, which is an intermediatepotential of source amplitude.

$\begin{matrix}{V_{SB} = \frac{V_{s +} + V_{s -}}{2}} & \left\lbrack {{Equation}\mspace{14mu} 4} \right\rbrack\end{matrix}$

It is understood from the above that with no leakage from the TFT 5 andother parts, the source holding potential during the vertical blankinginterval should be set to an intermediate potential of source amplitude.

The second case is when the TFT 5 and other parts leak. Conversely, thiscase is assumed to be under no influence at all of the parasiticcapacitance C_(DS). The leak components of the TFT 5 and other parts areroughly divided into those that leak to the common potential via theliquid crystal itself, and those that leak via the drain electrode 6 ofthe TFT 5. For brevity, those that leak to the common potential via theliquid crystal itself are regarded as resistance R_(LC), and those thatleak via the drain electrode 6 of the TFT 5 are regarded as resistanceR_(DS) in this embodiment.

When the vertical blanking interval is infinitely long, the resistanceR_(LC) and the resistance R_(DS) are connected in series between thecommon potential V_(COM) and the source holding potential V_(SB) duringthe vertical blanking interval, causing the source holding potentialV_(SB) to converge to a voltage divided by the respective resistances. Atime response of the convergence in such simple discharge circuit can besimply calculated by the magnitude of each resistance and the totalcapacitance of the pixel 2, the common potential V_(COM), and the sourceholding potential V_(SB).

Thus when the source holding potential V_(SB) is different from thecommon potential V_(COM), the potentials of pixels connected to the samesource line 4 after the lapse of the infinite time assume positivepolarity or negative polarity different from the common potentialV_(COM).

If the source holding potential V_(SB) is set to the aforementionedsource intermediate potential under the influence of the parasiticcapacitance C_(DS), the source holding potential V_(SB) is set higherthan the common potential V_(COM) by the feed-through voltage(ΔV_(CGD)). The result is that the source holding potential V_(SB)constantly deviates to positive polarity potential during the verticalblanking interval, resulting in image persistence and the like. In viewof only the leak components, it is ideal for the source holdingpotential V_(SB) to be set to the common potential V_(COM).

As described above, a value required for the source holding potentialV_(SB) varies depending on the parasitic capacitance C_(DS) componentsand leak components. Specifically, the source holding potential V_(SB)should be calculated to avoid deviation of average pixel potential basedon the relationship between the resistance R_(LC), the resistanceR_(DS), the parasitic capacitance C_(DS), the parasitic capacitanceC_(GD), the vertical period, and the vertical blanking interval.Although not easy algebraically, an optimum source holding potentialV_(SB) can be readily obtained by numerical calculation using a circuitsimulator such as SPICE. Without a circuit simulator, an optimum sourceholding potential V_(SB) may be determined by making fine adjustmentswith actual equipment based on the degree of image persistence andflicker. The resulting optimum source holding potential V_(SB) takes ona value in a range between the source intermediate potential and thecommon potential.

In the liquid crystal display device according to this embodiment, asignal is supplied from the timing controller 9 to the source driver 12in a manner that allows the source potential to be controlled to any DCpotential almost the entire time during the vertical blanking intervalwith a commonly available source driver IC having the charge sharingfunction. Therefore, a unique image can be obtained regardless of thesource potential in the last row, and power consumption is reducedbecause the panel is driven with little power during the verticalblanking interval. This embodiment is thus adaptable enough to the lowframe frequency driving system.

Second Preferred Embodiment

In a typical liquid crystal display device, gate lines are driven by agate driver provided on one side of the gate lines. The waveform of agate signal thus becomes steep in the vicinity of the input side of agate line, and becomes gradual with increasing distance from the inputside due to the resistance and parasitic capacitance of the gate line.In a liquid crystal display device in which gate lines are driven bygate drivers provided on both sides of the gate lines, the waveform of agate signal becomes gradual in the vicinity of the center of a gate linewhen compared to the vicinity of the input side.

The gradual waveform of a gate signal causes the gate signal to vary ina horizontal direction (gate line direction) of the liquid crystaldisplay device. The gate signal variations cause the feed-throughvoltage (ΔV_(CGD)) of a source potential to vary in the horizontaldirection of the liquid crystal display device. More specifically, whenthe waveform of a gate signal is steep, the feed-through voltage(ΔV_(CGD)) resulting from the parasitic capacitance C_(GD) cannot beraised to the source potential by charge movement via the TFT over aperiod of time during which the TFT is in an ON state and starts tobecome OFF. Namely, pixel potential cannot be raised to the sourcepotential by drain current of the TFT because the period of time duringwhich the TFT is in an ON state and starts to become OFF is short. Afeed-through voltage (ΔV_(CGD)) generated is thus proportionate to an ONvoltage Vgh of the gate—an OFF voltage Vgl of the gate (theproportionality coefficient is a value obtained by dividing theparasitic capacitance C_(GD) by the total capacitance of the pixel otherthan the parasitic capacitance C_(GD)).

When the waveform of a gate signal is gradual, on the other hand, pixelpotential can be raised to some extent toward the source potential bydrain current of the TFT even with the generation of a feed-throughvoltage (ΔV_(CGD)) because a period of time during which the TFT is inan ON state and starts to become OFF is long. The feed-through voltage(ΔV_(CGD)) is thus smaller in a position of the gradual gate signalwaveform than in a position of the steep gate signal waveform.

The aforementioned phenomenon means variations in an ideal commonpotential of a pixel in the horizontal direction of the liquid crystaldisplay device, which contributes to the generation of flicker, imagepersistence and the like.

As described in the first preferred embodiment, potential applied to asource line can be set to any potential during the vertical blankinginterval in the present invention. This allows the source holdingpotential during the vertical blanking interval to vary source line bysource line or in units of groups of source lines, in the horizontaldirection of the liquid crystal display device. The group of sourcelines refers to a unit of a plurality of source lines divided so thatsource lines supplied with positive polarity voltage and source linessupplied with negative polarity voltage are almost equal in number.

To provide a detailed description, it is assumed that the absolute valueof the feed-through voltage (ΔV_(CGD)) varies in such a way as shown inFIG. 9 in the horizontal direction of the liquid crystal display device.Since the feed-through voltage (ΔV_(CGD)) acts to reduce pixelpotential, the absolute value of the feed-through voltage (ΔV_(CGD))decreases and the pixel potential increases in a distant position fromthe gate driver. The amplitude thus increases on the positive polarityside and decreases on the negative polarity side in the distant positionfrom the gate driver, resulting in deviation of a DC component.

In the liquid crystal display device according to this embodiment, thesource holding potential V_(SB) is caused to vary in such a way as shownin FIG. 10 during the vertical blanking interval in the horizontaldirection of the liquid crystal display device. This causes theaforementioned average pixel potential to have positive correlationrelative to the source holding potential V_(SB) assuming that theparasitic capacitance C_(DS), the parasitic leak resistance R_(DS), andfurther the vertical period and the vertical blanking interval haveconstants. The pixel potential thus increases in the distant positionfrom the gate driver. The pixel potential thus increases in a distantposition from the gate driver. Therefore, the deviation of the DCcomponent can be compensated by setting the source holding potentialV_(SB) in a manner that compensates for the aforementioned reduction ofthe feed-through voltage (ΔV_(CGD)).

As a method for varying the source holding potential V_(SB) in thehorizontal direction of the liquid crystal display device, data to beapplied source line by source line or in units of groups of source linesin the horizontal direction is written with predetermined voltage duringthe first signal interval shown in FIG. 6. Data of the predeterminedvoltage may be recorded beforehand in a non-volatile memory and the likeand used or, when capacitance for holding data of all columns increasescost, may be recorded through discretization to some degree and used bylinear interpolation and the like.

There is a type of source driver IC in which a short circuit isestablished among all lines instead of between adjoining lines asillustrated in FIG. 5 to effect the charge sharing function. Such sourcedriver IC has the NOSW 21 provided between the 2n+1 output buffer 15 andthe 2(n+1) output buffer 15 shown in FIG. 5. In this type of sourcedriver IC, it is impossible to minutely control the source holdingpotential V_(SB) in the horizontal direction of the liquid crystaldisplay device. Yet a typical liquid crystal display device includes aplurality of source driver ICs, without performing charge sharing amongthe source driver ICs. So the source holding potential V_(SB) will varyat least with source driver ICs. In all cases, it is required that thenumber of source lines applied with data of positive polarity and thenumber of source lines applied with data of negative polarity be almostequal in a group of source lines that performs charge sharing.

A source holding potential V_(SB) set in order to compensate for thechange in feed-through voltage (ΔV_(CGD)) shown in FIG. 9 may bepredetermined by numerical calculation or by real adjustments when avertical blanking interval and other intervals have been uniquelydetermined. When a vertical blanking interval or one vertical period isunknown (these may vary in a certain range), however, a source holdingpotential V_(SB) to be set cannot be predetermined. In such cases,optimum source holding potentials V_(SB) for several vertical blankingintervals and one vertical periods are determined and stored in a table.This allows an applicable optimum source holding potentials V_(SB) to beobtained by detecting the vertical blanking interval and one verticalperiod during the actual operation of the liquid crystal display device.

FIG. 11 is a block diagram of the structure of the timing controller 9that executes the above method. A control signal generator 31 in FIG. 11has function as a typical timing controller, and also the function ofgenerating the control signal (latch signal LP) to effect the chargesharing function by outputting data predetermined during the verticalblanking interval. The data predetermined during the vertical blankinginterval is input to the control signal generator 31 from ablanking-interval-output-data generator 32. In the FIG. 11 example, asignal period detector 33 detects the vertical blanking interval or onevertical period from an input signal, and theblanking-interval-output-data generator 32 selects a plurality of tables35 loaded from a non-volatile memory 34 based on the detection result,to determine the predetermined data.

When the data stored in the table 35 are discretized, a linearinterpolation method and the like may be used between the data. Thestructure illustrated in FIG. 11 may be used to vary the source holdingpotential V_(SB) in the horizontal direction of the liquid crystaldisplay device according to this embodiment, and is also applicable tothe first preferred embodiment.

In addition to the compensation for the feed-through voltage (ΔV_(CGD))described above, the method according to this embodiment is of courseapplicable to compensation for deviation of pixel potential resultingfrom other factors that vary in the horizontal direction of the liquidcrystal display device. That is, deviation of a DC component of pixelpotential in the horizontal direction of the liquid crystal displaydevice can be suppressed only by the appropriate generation of a signalfrom the timing controller 9.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

1. A liquid crystal display device comprising: pixels arranged in amatrix on a translucent substrate; gate lines and source lines providedin a corresponding manner to said pixels; an active element at anintersection of each of said gate lines and each of said source lines,said active element having a drain electrode connected to said pixel; agate driver circuit supplying a gate signal to said gate lines; a sourcedriver circuit supplying source signals to said source lines so thatsource signals having a positive polarity voltage relative to a commonpotential of said pixels and source signals having a negative polarityvoltage relative to said common potential are almost equal in numberduring one horizontal interval; and a timing controller circuitsupplying prescribed signals to said gate driver circuit and said sourcedriver circuit to control said circuits, wherein a vertical blankinginterval includes: a setting data output interval, a short circuitinterval after said setting data output interval, and a holding intervalafter said short circuit interval, said source driver circuit, duringsaid setting data output interval, conducts a prescribed operation ofsupplying each of said source signals of positive polarity and negativepolarity with a prescribed voltage to said source lines to graduallychange voltages of said source lines, said source driver circuit, duringsaid short circuit interval, electrically cuts said source lines offfrom an output buffer of the source driver circuit after the supply ofsaid source signals while establishing a short circuit between adjoiningsource lines of said source lines supplied with said source signals ofopposite polarities thereby causing said source lines to graduallychange to and then hold a source holding potential having a DC voltagevalue during said holding interval, and said source holding potential isset higher than said common potential of said pixels and lower than asource intermediate potential of said source signals of positivepolarity and negative polarity.
 2. The liquid crystal display deviceaccording to claim 1, wherein said source driver circuit repeats saidprescribed operation a plurality of times during said vertical blankinginterval.
 3. The liquid crystal display device according to claim 1,wherein said source driver circuit sets said prescribed voltage of eachof said source signals supplied during said vertical blanking intervalso that said source holding potential for said source lines decreases byan amount having a direct relationship with a distance of said sourcelines from said gate driver.
 4. The liquid crystal display deviceaccording to claim 3, wherein said source driver circuit sets saidprescribed voltage of each of said source signals for each of saidsource lines, based on said distance from said gate driver, to decreasea pixel potential.
 5. The liquid crystal display device according toclaim 3, wherein said direct relationship is a linear relationship. 6.The liquid crystal display device according to claim 1, wherein saidsource driver circuit divides said source lines into groups so thatsource lines supplied with positive polarity voltage and said sourcelines supplied with negative polarity voltage of each group are almostequal in number, and said source driver circuit sets said prescribedvoltage of each of said source signals supplied during said verticalblanking interval so that said source holding potential has a commonvalue for source lines of a common group and so that said source holdingpotential decreases for said groups by an amount having a directrelationship with a distance from said gate driver.
 7. The liquidcrystal display device according to claim 6, wherein said source drivercircuit sets said prescribed voltage of each of said source signals foreach of said groups, based on said distance from said gate driver, todecrease a pixel potential.
 8. The liquid crystal display deviceaccording to claim 6, wherein said direct relationship is a linearrelationship.
 9. The liquid crystal display device according to claim 1,wherein said timing controller circuit comprises a signal perioddetector for detecting a vertical period and said vertical blankinginterval from an input signal, and a blanking-interval-output-datagenerator for generating said prescribed voltage of each of said sourcesignals supplied during said vertical blanking interval based on aresult of said signal period detector.
 10. A method of driving a liquidcrystal display device, said device comprising: pixels arranged in amatrix on a translucent substrate; gate lines and source lines providedin a corresponding manner to said pixels; an active element at anintersection of each of said gate lines and each of said source lines,said active element having a drain electrode connected to said pixel; agate driver circuit supplying a gate signal to said gate lines; a sourcedriver circuit supplying source signals to said source lines so thatsource signals having a positive polarity voltage relative to a commonpotential of said pixels and source signals having a negative polarityvoltage relative to said common potential are almost equal in numberduring one horizontal interval; and a timing controller circuitsupplying prescribed signals to said gate driver circuit and said sourcedriver circuit to control said circuits, wherein a vertical blankinginterval includes: a setting data output interval, a short circuitinterval after said setting data output interval, and a holding intervalafter said short circuit interval, said method comprising: an outputstep of, during said setting data output interval, supplying each ofsaid source signals of positive polarity and negative polarity with aprescribed voltage to said source lines by said source driver circuit togradually change voltages of said source lines; a short-circuit step of,during said short circuit interval, electrically cutting said sourcelines off from an output buffer of said source driver circuit after thesupply of said source signals while establishing a short circuit betweenadjoining source lines of said source lines supplied with said sourcesignals of opposite polarities after said output step; and a holdingstep, during said holding interval, of causing said source lines to holda source holding potential having a DC voltage value after saidshort-circuit step, said source holding potential set higher than saidcommon potential of said pixels and lower than a source intermediatepotential of said source signals of positive polarity and negativepolarity, wherein the short-circuit step and the holding step includecausing said source lines to gradually change to and hold the sourceholding potential.